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ltc2293/ltc2292/ltc2291 1 229321f , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. input frequency (mhz) 0 snr (dbfs) 70 71 200 229321 ta02 69 68 50 100 150 72 features descriptio u applicatio s u typical applicatio u integrated dual 12-bit adcs sample rate: 65msps/40msps/25msps single 3v supply (2.7v to 3.4v) low power: 400mw/235mw/150mw 71db snr up to 70mhz input 85db sfdr up to 70mhz input 110db channel isolation at 100mhz multiplexed or separate data bus flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family 80msps: ltc2294 (12-bit), ltc2299 (14-bit) 65msps: ltc2293 (12-bit), ltc2298 (14-bit) 40msps: ltc2292 (12-bit), ltc2297 (14-bit) 25msps: ltc2291 (12-bit), ltc2296 (14-bit) 10msps: ltc2290 (12-bit), ltc2295 (14-bit) 64-pin (9mm 9mm) qfn package dual 12-bit, 65/40/25msps low power 3v adcs the ltc ? 2293/ltc2292/ltc2291 are 12-bit 65msps/ 40msps/25msps, low power dual 3v a/d converters de- signed for digitizing high frequency, wide dynamic range signals. the ltc2293/ltc2292/ltc2291 are perfect for demanding imaging and communications applications with ac performance that includes 71db snr and 85db sfdr for signals well beyond the nyquist frequency. dc specs include 0.3lsb inl (typ), 0.15lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.25lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.3v logic. an optional multiplexer allows both channels to share a digital output bus. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. ltc2293: snr vs input frequency, ?db, 2v range, 65msps + input s/h analog input a analog input b clk a clk b 12-bit pipelined adc core clock/duty cycle control output drivers ov dd ognd mux d11a d0a ov dd ognd 229321 ta01 d11b d0b + output drivers input s/h 12-bit pipelined adc core clock/duty cycle control wireless and wired broadband communication imaging systems spectral analysis portable instrumentation
ltc2293/ltc2292/ltc2291 2 229321f top view up package 64-lead (9mm 9mm) plastic qfn t jmax = 125 c, ja = 20 c/w exposed pad (pin 65) is gnd and must be soldered to pcb a ina + 1 a ina C 2 refha 3 refha 4 refla 5 refla 6 v dd 7 clka 8 clkb 9 v dd 10 reflb 11 reflb 12 refhb 13 refhb 14 a inb C 15 a inb + 16 48 da5 47 da4 46 da3 45 da2 44 da1 43 da0 42 nc 41 nc 40 ofb 39 db11 38 db10 37 db9 36 db8 35 db7 34 db6 33 db5 65 64 gnd 63 v dd 62 sensea 61 vcma 60 mode 59 shdna 58 oea 57 ofa 56 da11 55 da10 54 da9 53 da8 52 da7 51 da6 50 ognd 49 ov dd gnd 17 v dd 18 senseb 19 vcmb 20 mux 21 shdnb 22 oeb 23 nc 24 nc 25 db0 26 db1 27 db2 28 db3 29 db4 30 ognd 31 ov dd 32 absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... C0.3v to 1v analog input voltage (note 3) ..... C0.3v to (v dd + 0.3v) digital input voltage .................... C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range ltc2293c, ltc2292c, ltc2291c ........... 0 c to 70 c ltc2293i, ltc2292i, ltc2291i ..........C40 c to 85 c storage temperature range ..................C65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number qfn part* marking ltc2293up ltc2292up ltc2291up ltc2293cup ltc2293iup ltc2292cup ltc2292iup ltc2291cup LTC2291IUP consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) ltc2293 ltc2292 ltc2291 parameter conditions min typ max min typ max min typ max units resolution 12 12 12 bits (no missing codes) integral linearity error differential analog input (note 5) C1.4 0.3 1.4 C1.4 0.3 1.4 C1.3 0.3 1.3 lsb differential differential analog input C0.8 0.15 0.8 C0.7 0.15 0.7 C0.7 0.15 0.7 lsb linearity error offset error (note 6) C12 212C12 212C12 212 mv gain error external reference C2.5 0.5 2.5 C2.5 0.5 2.5 C2.5 0.5 2.5 %fs offset drift 10 10 10 v/ c full-scale drift internal reference 30 30 30 ppm/ c external reference 15 15 15 ppm/ c gain matching external reference 0.3 0.3 0.3 %fs offset matching 2 2 2mv transition noise sense = 1v 0.25 0.25 0.25 lsb rms co verter characteristics u
ltc2293/ltc2292/ltc2291 3 229321f symbol parameter conditions min typ max units v in analog input range (a in + Ca in C ) 2.7v < v dd < 3.4v (note 7) 1v to 2v v v in,cm analog input common mode differential input (note 7) 1 1.5 1.9 v i in analog input leakage current 0v < a in + , a in C < v dd C1 1 a i sense sensea, senseb input leakage 0v < sensea, senseb < 1v C3 3 a i mode mode input leakage current 0v < mode < v dd C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) ltc2293 ltc2292 ltc2291 symbol parameter conditions min typ max min typ max min typ max units snr signal-to-noise ratio 5mhz input 71.3 71.4 71.4 db 12.5mhz input 70.1 71.2 db 20mhz input 69.6 71.3 db 30mhz input 69.6 71.3 db 70mhz input 71.3 71.1 70.9 db 140mhz input 71 70.7 70.6 db sfdr 5mhz input 90 90 90 db 12.5mhz input 75 90 db 20mhz input 74 90 db 30mhz input 74 90 db 70mhz input 85 85 85 db 140mhz input 80 80 80 db sfdr 5mhz input 90 90 90 db 12.5mhz input 80 90 db 20mhz input 79 90 db 30mhz input 78 90 db 70mhz input 90 90 90 db 140mhz input 90 90 90 db s/(n+d) 5mhz input 71.3 71.4 71.4 db 12.5mhz input 69.8 71.2 db 20mhz input 69.4 71.2 db 30mhz input 69.4 71.2 db 70mhz input 71.1 70.9 70.8 db 140mhz input 69.9 69.9 69.8 db i md f in = nyquist, 90 90 90 db nyquist + 1mhz crosstalk f in = nyquist C110 C110 C110 db a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) signal-to-noise plus distortion ratio intermodulation distortion spurious free dynamic range 4th harmonic or higher spurious free dynamic range 2nd or 3rd harmonic
ltc2293/ltc2292/ltc2291 4 229321f digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 30 ppm/ c v cm line regulation 2.7v < v dd < 3.3v 3 mv/v v cm output resistance C1ma < i out < 1ma 4 ? symbol parameter conditions min typ max units logic inputs (clk, oe, shdn, mux) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10 a 2.995 v i o = C200 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = C200 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
ltc2293/ltc2292/ltc2291 5 229321f power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 65mhz (ltc2293), 40mhz (ltc2292), or 25mhz (ltc2291), input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 65mhz (ltc2293), 40mhz (ltc2292), or 25mhz (ltc2291), input range = 1v p-p with differential drive. the supply current and power dissipation are the sum total for both channels with both channels active. note 9: recommended operating conditions. ltc2293 ltc2292 ltc2291 symbol parameter conditions min typ max min typ max min typ max units v dd analog supply (note 9) 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 v voltage ov dd output supply (note 9) 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 v voltage iv dd supply current both adcs at f s(max) 133 150 78 95 50 60 ma p diss power dissipation both adcs at f s(max) 400 450 235 285 150 180 mw p shdn shutdown power shdn = h, 2 2 2 mw (each channel) oe = h, no clk p nap nap mode power shdn = h, 15 15 15 mw (each channel) oe = l, no clk ltc2293 ltc2292 ltc2291 symbol parameter conditions min typ max min typ max min typ max units f s sampling frequency (note 9) 165140125mhz t l clk low time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t h clk high time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t ap sample-and-hold 0 0 0 ns aperture delay t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns t md mux to data delay c l = 5pf (note 7) 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns data access time c l = 5pf (note 7) 4.3 10 4.3 10 4.3 10 ns after oe bus relinquish time (note 7) 3.3 8.5 3.3 8.5 3.3 8.5 ns pipeline 6 6 6 cycles latency
ltc2293/ltc2292/ltc2291 6 229321f typical perfor a ce characteristics uw ltc2293: typical inl, 2v range, 65msps ltc2293: typical dnl, 2v range, 65msps ltc2293: 8192 point fft, f in = 5mhz, ?db, 2v range, 65msps ltc2293: 8192 point fft, f in = 30mhz, ?db, 2v range, 65msps ltc2293: 8192 point fft, f in = 70mhz, ?db, 2v range, 65msps ltc2293: 8192 point fft, f in = 140mhz, ?db, 2v range, 65msps ltc2293: grounded input histogram, 65msps ltc2293/ltc2292/ltc2291: crosstalk vs input frequency input frequency (mhz) 0 C130 crosstalk (db) C125 C120 C115 C110 C105 C100 20 40 60 80 229321 g01 100 code 0 3072 1024 2048 4096 inl error (lsb) 229321 g02 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 code 0 3072 1024 2048 4096 dnl error (lsb) 229321 g03 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 229321 g04 510152025 30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g05 510152025 30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g06 510152025 30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g07 510152025 30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g08 510152025 30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 code 70000 60000 50000 40000 30000 20000 10000 0 2043 61496 2044 229321 g09 2042 2123 count 1910 ltc2293: 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, ?db, 2v range 65msps
ltc2293/ltc2292/ltc2291 7 229321f typical perfor a ce characteristics uw ltc2293: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2293: snr and sfdr vs clock duty cycle, 65msps ltc2293: snr vs input level, f in = 30mhz, 2v range, 65msps ltc2293: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2293: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2293: sfdr vs input level, f in = 30mhz, 2v range, 65msps ltc2293: sfdr vs input frequency, ?db, 2v range, 65msps sample rate (msps) i ovdd (ma) 229321 g17 12 10 8 6 4 2 0 0 20 40 50 10 30 60 70 80 ltc2293: snr vs input frequency, ?db, 2v range, 65msps input frequency (mhz) 0 snr (dbfs) 70 71 200 229321 g10 69 68 50 100 150 72 sample rate (msps) i vdd (ma) 229321 g16 155 145 135 125 115 105 95 0 20 40 50 10 30 60 70 80 2v range 1v range input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 229321 g11 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 80 229321 g12 20 40 60 100 snr sfdr clock duty cycle (%) 30 snr and sfdr (dbfs) 60 229321 g13 40 50 70 100 95 90 85 80 75 70 65 35 45 55 65 sfdr: dcs on sfdr: dcs off snr: dcs on snr: dcs off input level (dbfs) C60 C50 snr (dbc and dbfs) C 40 C20 C30 C10 0 229321 g14 80 70 60 50 40 30 20 10 0 dbfs dbc input level (dbfs) C60 C50 C 40 C20 C30 C10 0 sfdr (dbc and dbfs) 229321 g15 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line
ltc2293/ltc2292/ltc2291 8 229321f typical perfor a ce characteristics uw ltc2292: 8192 point fft, f in = 30mhz, ?db, 2v range, 40msps ltc2292: 8192 point fft, f in = 70mhz, ?db, 2v range, 40msps ltc2292: 8192 point fft, f in = 140mhz, ?db, 2v range, 40msps ltc2292: 8192 point 2-tone fft, f in = 21.6mhz and 23.6mhz, ?db, 2v range, 40msps ltc2292: grounded input histogram, 40msps ltc2292: snr vs input frequency, ?db, 2v range, 40msps ltc2292: typical inl, 2v range, 40msps ltc2292: typical dnl, 2v range, 40msps ltc2292: 8192 point fft, f in = 5mhz, ?db, 2v range, 40msps code 0 inl error (lsb) 3072 229321 g18 1024 2048 4096 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 code 0 dnl error (lsb) 3072 229321 g19 1024 2048 4096 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 229321 g20 5101520 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g21 5101520 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g22 5101520 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g23 5101520 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g24 5101520 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 code 2050 count 229321 g25 2051 2052 70000 60000 50000 40000 30000 20000 10000 0 1424 61538 2558 input frequency (mhz) 0 snr (dbfs) 70 71 200 229321 g26 69 68 50 100 150 72
ltc2293/ltc2292/ltc2291 9 229321f ltc2292: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2292: i vdd vs sample rate, 5mhz sine wave input, ?db typical perfor a ce characteristics uw ltc2292: sfdr vs input level, f in = 5mhz, 2v range, 40msps ltc2291: typical inl, 2v range, 25msps ltc2291: typical dnl, 2v range, 25msps ltc2291: 8192 point fft, f in = 5mhz, ?db, 2v range, 25msps ltc2292: sfdr vs input frequency, ?db, 2v range, 40msps ltc2292: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2292: snr vs input level, f in = 5mhz, 2v range, 40msps sample rate (msps) 0 i vdd (ma) 40 229321 g31 10 20 30 50 100 90 80 70 60 2v range 1v range sample rate (msps) 0 i ovdd (ma) 4 6 40 229321 g32 2 0 10 20 30 50 8 input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 229321 g27 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 229321 g28 40 20 60 80 snr sfdr input level (dbfs) C60 C50 snr (dbc and dbfs) C 40 C20 C30 C10 0 229321 g29 80 70 60 50 40 30 20 10 0 dbfs dbc 229321 g30 input level (dbfs) C60 C50 C 40 C20 C30 C10 0 snr (dbc and dbfs) 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line code 0 inl error (lsb) 3072 229321 g33 1024 2048 4096 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 code 0 dnl error (lsb) 3072 229321 g34 1024 2048 4096 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 229321 g35 24 6810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120
ltc2293/ltc2292/ltc2291 10 229321f typical perfor a ce characteristics uw ltc2291: 8192 point 2-tone fft, f in = 10.9mhz and 13.8mhz, ?db, 2v range, 25msps ltc2291: grounded input histogram, 25msps ltc2291: snr vs input frequency, ?db, 2v range, 25msps ltc2291: sfdr vs input frequency, ?db, 2v range, 25msps ltc2291: snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db ltc2291: snr vs input level, f in = 5mhz, 2v range, 25msps ltc2291: 8192 point fft, f in = 30mhz, ?db, 2v range, 25msps ltc2291: 8192 point fft, f in = 70mhz, ?db, 2v range, 25msps ltc2291: 8192 point fft, f in = 140mhz, ?db, 2v range, 25msps frequency (mhz) 0 amplitude (db) 229321 g36 24 6810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g37 24 6810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g38 24 6810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 229321 g39 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 code count 2050 229321 g40 2048 2049 70000 60000 50000 40000 30000 20000 10000 0 61758 1607 2155 input frequency (mhz) 0 snr (dbfs) 70 71 200 229321 g41 69 68 50 100 150 72 input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 229321 g42 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 40 50 229321 g43 10 20 30 snr sfdr input level (dbfs) C60 C50 snr (dbc and dbfs) C 40 C20 C30 C10 0 229321 g44 80 70 60 50 40 30 20 10 0 dbfs dbc
ltc2293/ltc2292/ltc2291 11 229321f uu u pi fu ctio s a ina + (pin 1): channel a positive differential analog input. a ina (pin 2): channel a negative differential analog input. refha (pins 3, 4): channel a high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refla (pins 5, 6): channel a low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 10, 18, 63): analog 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. clka (pin 8): channel a clock input. the input sample starts on the positive edge. clkb (pin 9): channel b clock input. the input sample starts on the positive edge. reflb (pins 11, 12): channel b low reference. short together and bypass to pins 13, 14 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 13, 14 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. refhb (pins 13, 14): channel b high reference. short together and bypass to pins 11, 12 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 11, 12 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. a inb (pin 15): channel b negative differential analog input. a inb + (pin 16): channel b positive differential analog input. gnd (pins 17, 64): adc power ground. senseb (pin 19): channel b reference programming pin. connecting senseb to v cmb selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to senseb selects an input range of v senseb . 1v is the largest valid input range. v cmb (pin 20): channel b 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cma . ltc2291: i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v ltc2291: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2291: sfdr vs input level, f in = 5mhz, 2v range, 25msps typical perfor a ce characteristics uw sample rate (msps) i vdd (ma) 229321 g46 70 60 50 40 30 0 10 20 515 25 30 35 2v range 1v range 0 10 20 515 25 30 35 sample rate (msps) i ovdd (ma) 229321 g47 6 4 2 0 input level (dbfs) C60 C50 C 40 C20 C30 C10 0 sfdr (dbc and dbfs) 229321 g45 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line
ltc2293/ltc2292/ltc2291 12 229321f mux (pin 21): digital output multiplexer control. if mux is high, channel a comes out on da0-da13, ofa; channel b comes out on db0-db13, ofb. if mux is low, the output busses are swapped and channel a comes out on db0- db13, ofb; channel b comes out on da0-da13, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. shdnb (pin 22): channel b shutdown mode selection pin. connecting shdnb to gnd and oeb to gnd results in normal operation with the outputs enabled. connecting shdnb to gnd and oeb to v dd results in normal opera- tion with the outputs at high impedance. connecting shdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting shdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance. oeb (pin 23): channel b output enable pin. refer to shdnb pin function. nc (pins 24, 25, 41, 42): do not connect these pins. db0 ?db11 (pins 26 to 30, 33 to 39): channel b digital outputs. db11 is the msb. ognd (pins 31, 50): output driver ground. ov dd (pins 32, 49): positive supply for the output driv- ers. bypass to ground with 0.1 f ceramic chip capacitor. ofb (pin 40): channel b overflow/underflow output. high when an overflow or underflow has occurred. da0 ?da11 (pins 43 to 48, 51 to 56): channel a digital outputs. da11 is the msb. ofa (pin 57): channel a overflow/underflow output. high when an overflow or underflow has occurred. oea (pin 58): channel a output enable pin. refer to shdna pin function. shdna (pin 59): channel a shutdown mode selection pin. connecting shdna to gnd and oea to gnd results in normal operation with the outputs enabled. connecting shdna to gnd and oea to v dd results in normal opera- tion with the outputs at high impedance. connecting shdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting shdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance. mode (pin 60): output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects straight bi- nary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. v cma (pin 61): channel a 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cmb . sensea (pin 62): channel a reference programming pin. connecting sensea to v cma selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sensea selects an input range of v sensea . 1v is the largest valid input range. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. uu u pi fu ctio s
ltc2293/ltc2292/ltc2291 13 229321f fu n ctio n al block diagra uu w figure 1. functional block diagram (only one channel is shown) shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 229321 f01 input s/h sense v cm a in a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d11 d0
ltc2293/ltc2292/ltc2291 14 229321f dual digital output bus timing (only one channel is shown) ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ?5 n ?4 n ?3 n ?2 clk d0-d11, of 229321 td01 n ?6 n ?1 multiplexed digital output bus timing t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a ?6 b ?6 b ?6 a ?6 a ?5 b ?5 b ?5 a ?5 a ?4 b ?4 b ?4 a ?4 a ?3 b ?3 b ?3 a ?3 a ?2 b ?2 a + 2 a + 4 a + 3 a analog input a t h t d t md t l clka = clkb = mux d0a-d11a, ofa 229321 td02 d0b-d11b, ofb
ltc2293/ltc2292/ltc2291 15 229321f dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, applicatio s i for atio wu uu 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches midsupply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ) ? f in ? t jitter crosstalk crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a C1dbfs signal). converter operation as shown in figure 1, the ltc2293/ltc2292/ltc2291 are dual cmos pipelined multistep converters. the convert- ers have six pipelined adc stages; a sampled analog input will result in a digitized value six cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost
ltc2293/ltc2292/ltc2291 16 229321f sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2293/ltc2292/ ltc2291 have two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the applicatio s i for atio wu u u third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2293/ ltc2292/ltc2291 cmos differential sample-and-hold. the analog inputs are connected to the sampling capaci- tors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summa- tion of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, the inputs are reconnected to the sampling figure 2. equivalent input circuit v dd v dd v dd 15 ? 15 ? c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf ltc2293/ltc2292/ltc2291 a in + a in clk 229321 f02
ltc2293/ltc2292/ltc2291 17 229321f capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2293/ltc2292/ltc2291 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling applicatio s i for atio wu uu glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2293/ltc2292/ltc2291 being driven by an rf transformer with a center tapped second- ary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies be- low 1mhz. figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm ltc2293 ltc2292 ltc2291 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 229321 f03 figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies.
ltc2293/ltc2292/ltc2291 18 229321f figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. applicatio s i for atio wu uu figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz figure 8. recommended front end circuit for input frequencies above 300mhz figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 229321 f06 ltc2293 ltc2292 ltc2291 figure 5. single-ended drive figure 4. differential drive with an amplifier 25 ? 25 ? 12pf 2.2 f v cm 229321 f04 + + cm analog input high speed differential amplifier a in + a in ltc2293 ltc2292 ltc2291 25 ? 0.1 f analog input v cm a in + a in C 1k 12pf 229321 f05 2.2 f 1k 25 ? 0.1 f ltc2293 ltc2292 ltc2291 the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 229321 f07 ltc2293 ltc2292 ltc2291 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 229321 f08 6.8nh 6.8nh ltc2293 ltc2292 ltc2291
ltc2293/ltc2292/ltc2291 19 229321f applicatio s i for atio wu uu reference operation figure 9 shows the ltc2293/ltc2292/ltc2291 refer- ence circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage reference can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. each adc channel has an independent reference with its own bypass capacitors. the two channels can be used with the same or different input ranges. other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. for the best channel matching, connect an external reference to sensea and senseb. figure 10. 1.5v range adc figure 9. equivalent reference circuit v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 229321 f09 4 ? diff amp 1 f 1 f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control ltc2293/ltc2292/ltc2291 v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 229321 f10 ltc2293 ltc2292 ltc2291 input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 3.8db. see the typical performance charac- teristics section. driving the clock input the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low jitter squaring circuit before the clk pin (figure 11).
ltc2293/ltc2292/ltc2291 20 229321f applicatio s i for atio wu uu the noise performance of the ltc2293/ltc2292/ltc2291 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. it is recommended that clka and clkb are shorted together and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clka and clkb can be driven by two different signals. if this delay exceeds 1ns, the performance of the part may degrade. clka and clkb should not be driven by asynchronous signals. maximum and minimum conversion rates the maximum conversion rate for the ltc2293/ltc2292/ ltc2291 is 65msps (ltc2293), 40msps (ltc2292), and 25msps (ltc2291). for the adc to operate properly, the clk signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 7.3ns (ltc2293), 11.8ns (ltc2292), and 18.9ns (ltc2291) for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the mode pin controls both channel a and channel bthe duty cycle stabilizer is either on or off for both channels. the lower limit of the ltc2293/ltc2292/ltc2291 sample rate is determined by droop of the sample-and-hold cir- cuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junc- tion leakage will discharge the capacitors. the specified minimum operating frequency for the ltc2293/ltc2292/ ltc2291 is 1msps. digital outputs digital output buffers figure 12 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 ? to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters, the digi- tal output loading can affect the performance. the digital outputs of the ltc2293/ltc2292/ltc2291 should drive a minimal capacitive load to avoid possible interaction figure 11. sinusoidal single-ended clk drive clk 50 ? 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean supply sinusoidal clock input 229321 f11 nc7svu04 ltc2293 ltc2292 ltc2291
ltc2293/ltc2292/ltc2291 21 229321f between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the ltc2293/ltc2292/ltc2291 parallel digital output can be selected for offset binary or 2s complement format. note that mode controls both channel a and channel b. connecting mode to gnd or 1/3v dd selects straight binary output format. connecting mode to 2/3v dd or v dd selects 2s complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 1 shows the logic states for the mode pin. applicatio s i for atio wu u u overflow bit when of outputs a logic high the converter is either overranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. channels a and b have independent output enable pins (oea, oeb). table 1. mode pin function clock duty mode pin output format cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off figure 12. digital output buffer 229321 f12 ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to v dd predriver logic data from latch oe ltc2293/ltc2292/ltc2291
ltc2293/ltc2292/ltc2291 22 229321f applicatio s i for atio wu u u sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent shdn pins (shdna, shdnb). channel a is controlled by shdna and oea, and channel b is controlled by shdnb and oeb. the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operat- ing while the other channel is in nap or sleep mode. digital output multiplexer the digital outputs of the ltc2293/ltc2292/ltc2291 can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on da0-da11, ofa; channel b comes out on db0-db11, ofb. if mux is low, the output busses are swapped and channel a comes out on db0-db11, ofb; channel b comes out on da0-da11, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode). the multiplexed data is available on either data busthe unused data bus can be disabled with its oe pin. grounding and bypassing the ltc2293/ltc2292/ltc2291 requires a printed cir- cuit board with a clean, unbroken ground plane. a multi- layer board with an internal ground plane is recom- mended. layout for the printed circuit board should en- sure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc2293/ltc2292/ltc2291 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2293/ltc2292/ ltc2291 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal perfor- mance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area.
ltc2293/ltc2292/ltc2291 23 229321f c21 0.1 f c27 0.1 f v dd v dd v dd v dd v dd v cc v cmb c20 2.2 f c18 1 f c23 1 f c34 0.1 f c31 12pf c17 0.1 f c14 0.1 f c25 0.1 f c30 18pf l2 47nh r28 24 ? c32 18pf c28 2.2 f c35 0.1 f c24 0.1 f c36 4.7 f e3 v dd 3v e5 pwr gnd v dd v cc v cc 228876 ai01 c1 0.1 f r16 33 ? r1 1k r2 1k r3 1k r10 1k r14 49.9 ? r20 24.9 ? r18 24.9 ? r24 24.9 ? r17 opt r22 24.9 ? r23 51 t2 etc1-1t c29 0.1 f c33 0.1 f j3 clock input u6 nc7svu04 u4 nc7sv86p5x u7 nc7sv86p5x u3 nc7svu04 c13 0.1 f c15 0.1 f c12 4.7 f 6.3v l1 bead v dd c19 0.1 f c11 0.1 f c4 0.1 f c2 2.2 f c10 2.2 f c9 1 f c13 1 f r15 1k j4 analog input b v cc 1 2 3 4 ?? 5 v cmb c8 0.1 f c6 12pf c44 0.1 f r6 24.9 ? r5 24.9 ? r9 24.9 ? r4 opt r7 24.9 ? r8 51 t1 etc1-1t c3 0.1 f c7 0.1 f j2 analog input a 1 2 3 5 ?? 4 v cma v cma 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp1 mode c16 0.1 f 25 23 27 29 31 33 35 37 39 21 19 15 17 13 9 7 1 3 5 2 4 11 26 24 30 28 34 32 38 40 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 3201s-40g1 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 36 22 20 16 18 14 10 8 6 12 r13 10k r11 10k r12 10k r30 15 ? r n1d 33 ? r n1c 33 ? r n1b 33 ? r n1a 33 ? r n2d 33 ? r n2c 33 ? r n2b 33 ? r n2a 33 ? r n3d 33 ? r n3c 33 ? r n3b 33 ? r n3a 33 ? r n4d 33 ? r n4c 33 ? r n4b 33 ? c39 1 f c38 0.01 f v cc v dd byp gnd adj out shdn gnd in 1 2 3 4 8 u8 lt1763 7 6 5 gnd r26 100k r25 105k c37 10 f 6.3v e4 gnd c40 0.1 f c41 0.1 f a ina + a ina C refha refha refla refla v dd clka clkb v dd reflb reflb refhb refhb a inb C a inb + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 da5 da4 da3 da2 da1 da0 nc nc ofb db11 db10 db9 db8 db7 db6 db5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd v dd sensea vcma mode shdna oea ofa da11 da10 da9 da8 da7 da6 ognd ov dd gnd v dd senseb vcmb mux shdnb oeb nc nc db0 db1 db2 db3 db4 ognd ov dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e2 ext ref b 12 v dd 34 v cm v dd v cmb 56 ext ref jp3 sense e1 ext ref a 12 v dd 34 v cm v dd 56 ext ref jp2 sense a c5 0.1 f c26 0.1 f v cc b3 b2 b4 b5 b6 b7 oe b1 b0 a3 a1 a0 18 17 16 15 14 13 12 11 19 2 20 v cc 74vcx245bqx v cc 3 4 5 6 7 8 9 1 10 a2 a7 t/r gnd a5 a4 a6 b3 b2 b4 b5 b6 b7 oe b1 b0 a3 a1 a0 18 17 16 15 14 13 12 11 19 2 20 v cc 74vcx245bqx v cc 3 4 5 6 7 8 9 1 10 a2 a7 t/r gnd a5 a4 a6 a0 a1 a2 a3 v cc wp scl sda 1 2 3 4 8 7 6 5 r29 51 ? l4 47nh c43 8.2pf l3 47nh c42 8.2pf u5 24lc025 v cc r31 tbd r27 tbd v cc u10 nc7sv86p5x r32 22 ? u1 ltc2293 applicatio s i for atio wu u u
ltc2293/ltc2292/ltc2291 24 229321f applicatio s i for atio wu u u silkscreen top top side
ltc2293/ltc2292/ltc2291 25 229321f applicatio s i for atio wu u u inner layer 2 gnd inner layer 3 power
ltc2293/ltc2292/ltc2291 26 229321f applicatio s i for atio wu u u bottom side
ltc2293/ltc2292/ltc2291 27 229321f package descriptio u up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom view?xposed pad 7.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (up64) qfn 1003 recommended solder pad pitch and dimensions 0.70 0.05 7.15 0.05 (4 sides) 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc2293/ltc2292/ltc2291 28 229321f related parts part number description comments ltc1403a/ltc1403 14-bit/12-bit 2.8msps serial adc 3v, 14mw, differential input, msop package ltc1407a/ltc1407 14-bit/12-bit 3msps, simultaneous sampling serial adc 3v, 14mw, 2-ch. differential input, msop package ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps wideband adc up to 500mhz if undersampling, 90db sfdr ltc2225 12-bit, 10msps adc 60mw, 71db snr, 5mm 5mm qfn ltc2226 12-bit, 25msps adc 75mw, 71db snr, 5mm 5mm qfn ltc2227 12-bit, 40msps adc 125mw, 71db snr, 5mm 5mm qfn ltc2228 12-bit, 65msps adc 205mw, 71db snr, 5mm 5mm qfn ltc2229 12-bit, 80msps adc 211mw, 70.6db snr, 5mm 5mm qfn ltc2236 10-bit, 25msps adc 75mw, 61db snr, 5mm 5mm qfn ltc2237 10-bit, 40msps adc 125mw, 61db snr, 5mm 5mm qfn ltc2238 10-bit, 65msps adc 205mw, 61db snr, 5mm 5mm qfn ltc2239 10-bit, 80msps adc 211mw, 61db snr, 5mm 5mm qfn ltc2245 14-bit, 10msps adc 60mw, 74.4db snr, 5mm 5mm qfn ltc2246 14-bit, 25msps adc 75mw, 74db snr, 5mm 5mm qfn ltc2247 14-bit, 40msps adc 125mw, 74db snr, 5mm 5mm qfn ltc2248 14-bit, 65msps adc 205mw, 74db snr, 5mm 5mm qfn ltc2249 14-bit, 80msps adc 222mw, 73db snr, 5mm 5mm qfn ltc2286 dual 10-bit, 25msps adc 150mw, 61db snr, 9mm 9mm qfn ltc2287 dual 10-bit, 40msps adc 235mw, 61db snr, 9mm 9mm qfn ltc2288 dual 10-bit, 65msps adc 400mw, 61db snr, 9mm 9mm qfn ltc2289 dual 10-bit, 80msps adc 445mw, 61db snr, 9mm 9mm qfn ltc2290 dual 12-bit, 10msps adc 120mw, 71db snr, 9mm 9mm qfn ltc2294 dual 12-bit, 80msps adc 445mw, 70.6db snr, 9mm 9mm qfn ltc2295 dual 14-bit, 10msps adc 120mw, 74.4db snr, 9mm 9mm qfn ltc2296 dual 14-bit, 25msps adc 150mw, 74db snr, 9mm 9mm qfn ltc2297 dual 14-bit, 40msps adc 235mw, 74db snr, 9mm 9mm qfn ltc2298 dual 14-bit, 65msps adc 400mw, 74db snr, 9mm 9mm qfn ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm 9mm qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver 450mhz 1db bw, 47db oip3, digital gain with digitally controlled gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator 20dbm iip3, integrated lo quadrature generator lt5516 0.8ghz to 1.5ghz direct conversion quadrature demodulator 21.5dbm iip3, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator 21dbm iip3, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 ? single ended rf and lo ports linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/tp 1204 1k ? printed in usa

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